Semiconductor device with substantial driving current and decreased junction leakage current

ABSTRACT

The semiconductor device includes an active region, a stepped recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate. The stepped recess channel region is formed in the active region. The vertical silicon-on-insulator (SOI) channel structures are disposed at sidewalls of both device isolation structures in a longitudinal direction of a gate region. The gate insulating film is disposed over the active region including the stepped recess channel region. The gate structure is disposed over the stepped recess channel region of the gate region.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application is a division of U.S. patent application Ser. No. 11/480,866 filed on Jul. 6, 2006, now U.S. Pat. No. 7,432,162, issued on Oct. 7, 2008, which claims priority to Korean patent application number 10-2006-0026512, filed on Mar. 23, 2006, which are incorporated by reference in their entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a memory device. More particularly, the present invention relates to a semiconductor device and a method for fabricating the same having a stepped recess channel region including vertical silicon-on-insulator (SOI) channel structures.

When a channel length of a cell transistor is decreased, the ion concentration of a cell channel region is generally increased in order to maintain the threshold voltage of the cell transistor. An electric field in source/drain regions of the cell transistor is enhanced to increase leakage current. This results in degradation of the refresh characteristics of a dynamic random access memory (DRAM) structure. Therefore, there is a need for semiconductor devices in which the refresh characteristics are improved.

FIG. 1 is a simplified layout of a semiconductor device, wherein reference numerals 1 and 3 denote an active region, which is defined by a device isolation structure 30, and a gate region, respectively.

FIGS. 2 a through 2 c are simplified cross-sectional views illustrating a method for fabricating a semiconductor device, wherein FIGS. 2 a through 2 c are cross-sectional views taken along the line I-I′ of FIG. 1.

Referring to FIG. 2 a, a semiconductor substrate 10 having a pad insulating film (not shown) is etched using a device isolation mask (not shown) to form a trench (not shown) defining a Fin-type active region 20. An insulating film for device isolation (not shown) is formed to fill the trench. The insulating film for device isolation is polished until the pad insulating film is exposed to form a device isolation structure 30. The pad insulating film is removed to expose the top surface of the Fin-type active region 20.

Referring to FIG. 2 b, a predetermined thickness of the device isolation structure 30 is etched using a recess gate mask (not shown) defining a gate region 3 shown in FIG. 1 to protrude an upper part of the Fin-type active region 20 over the device isolation structure 30.

Referring to FIG. 2 c, a gate insulating film 60 is formed over the protruded Fin-type active region 20. A gate structure 90 is formed over the gate insulating film 60 of the gate region 3 shown in FIG. 1 to fill the protruded Fin-type active region 20, wherein the gate structure 90 comprises a stacked structure of a gate electrode 70 and a gate hard mask layer pattern 80.

FIG. 3 is a simplified cross-sectional view illustrating a semiconductor device. Referring to FIG. 3, if a voltage above the threshold voltage is applied to the gate, an inversion layer IL and a depletion region DR are formed in a semiconductor substrate 10 under the gate insulating film 60.

According to the above method for fabricating a semiconductor device, it is difficult to secure On/Off characteristics of the cell transistor due to shrinkage of its channel length. Since the channel area of the device is limited, it is also difficult to obtain substantial driving current. Even through the Fin FET structure of the cell transistor (trigate) has been proposed in order to secure the channel area of the device, there are problems of lowering its threshold voltage, degrading its refresh characteristics, and increasing the degree of process complexity such as the process of etching the device isolation structure.

BRIEF SUMMARY OF THE INVENTION

The present invention relates to a semiconductor device and a method for fabricating the same wherein a stepped recess channel region including vertical silicon-on-insulator (SOI) channel structures, which are disposed at sidewalls of both device isolation structures under a gate in a longitudinal direction of a gate region, is formed, thereby securing substantial driving current and decreasing its junction leakage current. Accordingly, the short channel effect (SCE) and refresh characteristics of the device can be improved.

According to an embodiment of the present invention, a semiconductor device includes: a device isolation structure formed in a semiconductor substrate to define an active region; a stepped recess channel region including vertical silicon-on-insulator (SOI) channel structures formed in the active region, wherein the vertical SOI channel structures are disposed at sidewalls of both device isolation structures in a longitudinal direction of a gate region; and a gate structure disposed over the stepped recess channel region of the gate region.

According to another embodiment of the present invention, a method for fabricating a semiconductor device includes: (a) forming a device isolation structure in a semiconductor substrate having a pad insulating film; (b) selectively etching the pad insulating film by a recess gate mask to expose the semiconductor substrate of a recess region; (c) forming a spacer at a sidewall of the recess region; (d) etching a predetermined thickness of the semiconductor substrate exposed at the lower part of the recess region using the spacer as an etching mask to form a first recess; (e) removing the spacer to expose its underlying semiconductor substrate; (f) etching a predetermined thickness of the exposed semiconductor substrate to form a second recess, wherein a stepped recess channel region including vertical silicon-on-insulator (SOI) channel structures is formed at the lower part of the second recess, wherein the vertical SOI channel structures are formed at sidewalls of both device isolation structures in the longitudinal direction of a gate region; (g) removing the pad insulating film to expose the semiconductor substrate including the stepped recess channel region; (h) forming a gate insulating film over the exposed semiconductor substrate; and (i) forming a gate structure over the gate insulating film of the gate region, wherein the gate structure includes a stacked structure of a gate electrode filling the recess channel region and a gate hard mask layer pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified layout of a semiconductor device.

FIGS. 2 a through 2 c are simplified cross-sectional views illustrating a method for fabricating a semiconductor device.

FIG. 3 is a simplified cross-sectional view illustrating a semiconductor device.

FIG. 4 is a simplified layout of a semiconductor device according to an embodiment of the present invention.

FIGS. 5( i), 5(ii), and 7 are simplified cross-sectional views illustrating a semiconductor device according to an embodiment of the present invention.

FIGS. 6 a through 6 j are simplified cross-sectional views illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention.

DESCRIPTION OF SPECIFIC EMBODIMENTS

The present invention relates to a semiconductor device and a method for fabricating the same wherein a stepped recess channel region including vertical silicon-on-insulator (SOI) channel structures, which are disposed at sidewalls of both device isolation structures under a gate in a longitudinal direction of a gate region, is formed, thereby securing substantial driving current and decreasing its junction leakage current. Accordingly, the short channel effect (SCE) and refresh characteristics of the device can be improved.

FIG. 4 is a simplified layout of a semiconductor device according to an embodiment of the present invention, wherein reference numerals 101 and 103 denote an active region defined by the device isolation structure 130 and a gate region, respectively.

FIGS. 5( i) and 5(ii) are simplified cross-sectional views of a semiconductor device according to an embodiment of the present invention, wherein FIG. 5( i) is a cross-sectional view taken along a longitudinal direction in accordance with the line I-I′ of FIG. 4 and FIG. 5( ii) is a cross-sectional view taken along a latitudinal direction in accordance with the line II-II′ of FIG. 4.

Referring to FIGS. 5( i) and 5(ii), a device isolation structure 130 defining the active region 101 shown in FIG. 4 is formed in a semiconductor substrate 110. A stepped recess channel region (L1+L2+L3) is formed in the active region 101 shown in FIG. 4. In one embodiment of the present invention, the stepped recess channel region (L1+L2+L3) includes vertical silicon-on-insulator (SOI) channel structures 165, which are disposed at sidewalls of both device isolation structures 130 in a longitudinal direction of a gate region 103 shown in FIG. 4. In addition, the stepped recess channel region (L1+L2+L3) includes vertical channel regions L1 and L3 and a horizontal channel region L2 in a longitudinal direction of the active region 101 of FIG. 4. In another embodiment, a thickness of the vertical SOI channel structure 165 in a longitudinal direction of the gate region 103 shown in FIG. 4 ranges from about 1 nm to about 50 nm in a horizontal direction. In addition, a depth of the vertical SOI channel structure 165 from the upper step of the stepped recess channel region to its lower step ranges from about 5 nm to about 200 nm in a vertical direction.

In addition, a gate insulating film 160 is disposed over the active region 101 of FIG. 4 including the stepped recess channel region. A gate structure 190 corresponding the gate region 103 (FIG. 4) is disposed over the gate insulating film 160. Spacers (not shown) are formed at both sidewalls of the gate structure 190. Source/drain regions 195 are formed in the semiconductor substrate 110 between the gate structures 190. In one embodiment of the present invention, the gate structure 190 includes a stacked structure of a gate electrode 170 filling the stepped recess channel region and a gate hard mask layer pattern 180. The gate electrode 170 includes a stacked structure of a lower gate electrode (not shown) and an upper gate electrode (not shown). In another embodiment of the present invention, the lower gate electrode is a polysilicon layer doped with impurity ions such as P or B. The upper gate electrode is selected from the group consisting of a titanium (Ti) layer, a titanium nitride (TiN) film, a tungsten (W) layer, an aluminum (Al) layer, a copper (Cu) layer, a tungsten silicide (WSi_(X)) layer or combinations thereof.

FIG. 7 is a simplified cross-sectional view illustrating a semiconductor device according to the present invention, which shows in detail the stepped recess channel region under the gate structure 190.

Referring to FIG. 7, the stepped recess channel region includes vertical SOI channel structures disposed at sidewalls of both device isolation structures 130 in a longitudinal direction of the gate region 103 shown in FIG. 4. When voltage above the threshold voltage is applied to a gate, an inversion layer IL and a depletion region DR are formed in the stepped recess channel region including the vertical SOI channel structures. As a result, the lowering of threshold voltage due to decreased number of charges in the depletion region can be overcome by the stepped recess channel region. Since a contact area between the stepped channel region and the source/drain regions 195 is decreased due to shrinkage of channel thickness, leakage current of the source/drain regions 195 can be reduced. Accordingly, refresh characteristics of the device can be improved. In addition, a complete depletion region is formed because of the thin vertical SOI channel structures, which results in improving the short channel effect (SCE) of the device.

Accordingly, it can be realized with improvement of the short channel effect (SCE) of the device, increase in its driving current, and minimizing its leakage current.

FIGS. 6 a through 6 j are simplified cross-sectional views illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein FIGS. 6 a(i) through 6 j(i) are cross-sectional views taken along a longitudinal direction in accordance with the line I-I′ of FIG. 4 and FIGS. 6 a(ii) through 6 j(ii) are cross-sectional views taken along a latitudinal direction in accordance with the line II-II′ of FIG. 4.

Referring to FIG. 6 a, a pad oxide film 113 and a pad nitride film 115 are formed over a semiconductor substrate 110. The pad nitride film 115, the pad oxide film 113, and the semiconductor substrate 110 are etched using a device isolation mask (not shown) as an etching mask to form a trench (not shown) defining an active region. An insulating film for device isolation (not shown) is formed over an entire surface of the resulting structure to fill up the trench. The insulating film for device isolation is polished until the pad nitride film 115 is exposed to form a device isolation structure 130. In one embodiment of the present invention, the insulating film for device isolation is a silicon oxide film. In addition, a polishing process for the device isolation structure 130 is performed by a chemical mechanical polishing (CMP) method.

Referring to FIGS. 6 b through 6 d, the pad nitride film 115 and the pad oxide film 113 are etched using a recess gate mask (not shown) defining a gate region 103 shown in FIG. 4 as an etching mask to expose the semiconductor substrate 110 of a recess region 135. An insulating film 140 is formed over an entire surface of the resulting structure. The insulating film 140 is etched to form a spacer 145 on a sidewall of the recess region 135. In one embodiment of the present invention, the insulating film 140 is selected from the group consisting of a silicon nitride film, a silicon oxide film, a polysilicon layer or combinations thereof with its thickness ranging from about 1 nm to about 50 nm. In addition, a process for forming the insulating film 140 is performed by a chemical vapor deposition (CVD) method using a source gas including SiH₄, O₂, N₂O, Si(OC₂H₅)₄, SiH₂Cl₂, NH₃, N₂, He or combinations thereof. Further, the etching process for the spacer 145 is performed by a plasma etching method using a gas including C_(x)F_(y)H_(z), O₂, HCl, Ar, He or combinations thereof.

Referring to FIGS. 6 e and 6 f, the semiconductor substrate 110 exposed at the lower part of the recess region 135 is etched using the spacer 145 as an etching mask to form a first recess 150. A buffer film 153 is formed an entire surface of the resulting structure to fill up the first recess 150. In one embodiment of the present invention, a depth of the etched semiconductor substrate 110 ranges from about 10 nm to about 500 nm. In addition, the buffer film 153 is formed of a predetermined material, which has etching selectivity greater than that of a silicon oxide film or a silicon nitride film. The predetermined material for the buffer film 153 is selected from the group consisting of a Spin-on glass (SOG) film, a borosilicate glass (BSG) film, a phosphosilicate glass (PSG) film, a borophosphosilicate glass (BPSG) film, or combinations thereof.

Referring to FIGS. 6 g through 6 i, the buffer film 153 is selectively etched so that a predetermined thickness of the buffer film 153 remains at the lower part of the first recess 150. The spacer 145 is removed to expose the semiconductor substrate 110 between the pad nitride film 115 and the remaining buffer film 153. A predetermined thickness of the exposed semiconductor substrate 110 is etched to form a second recess 155. The remaining buffer film 153 is removed to form a stepped recess channel region (L1+L2+L3). The pad nitride film 115 and the pad oxide film 113 are removed to expose the semiconductor substrate 110 including the stepped recess channel region (L1+L2+L3). In one embodiment of the present invention, the stepped recess channel region (L1+L2+L3) includes vertical silicon-on-insulator (SOI) channel structures 165, which are formed at sidewalls of both device isolation structures 130 in a longitudinal direction of the gate region 103 shown in FIG. 4. In addition, the etching process for the buffer film 153 is performed using a solution including HF. In another embodiment, the etching process for the second recess 155 is performed by i) a plasma etching method using a gas including F₂ or Cl₂, ii) a dry etching method using a gas including HCl, iii) a wet etching method using a solution including NH₄OH or KOH, or iv) combinations thereof. In addition, a depth of the etched semiconductor substrate 110 ranges from about 10 nm to about 500 nm during the process of forming the second recess 155. A depth of the vertical SOI channel structure V from the upper step of the stepped recess channel region to its lower step ranges from about 5 nm to about 200 nm in a vertical direction.

According to another embodiment of the present invention, the buffer film 153 is etched until the pad nitride film 115 is exposed. The spacer 145 between the buffer film 153 and the pad nitride film 115 is selectively removed to expose its underlying semiconductor substrate 110. The exposed semiconductor substrate 110 and the buffer film 153 are simultaneously etched to form a second recess 155. Next, the remaining buffer film 153 at the lower part of the second recess 155 is selectively removed to form a stepped recess channel region (L1+L2+L3). At this time, the stepped recess channel region includes vertical silicon-on-insulator (SOI) channel structures 165, which are formed at sidewalls of both device isolation structures 130 in a longitudinal direction of the gate region 103 shown in FIG. 4. Thereafter, the pad nitride film 115 and the pad oxide film 113 are removed to expose the semiconductor substrate 110 including the stepped recess channel region (L1+L2+L3).

Accordingly, a semiconductor device having the stepped recess channel region, which is combined with vertical SOI channel and recess channel structures; is designed in accordance with one embodiment of the present invention, thereby securing substantial driving current and decreasing junction leakage current of the device. As a result, the short channel effect (SCE) and refresh characteristics of the device can be improved.

Referring to FIG. 6 j, a gate insulating film 160 is formed over the exposed semiconductor substrate 110. A lower gate conductive layer (not shown) is formed over an entire surface of the resulting structure to fill up the second recess 155. An upper gate conductive layer (not shown) and a gate hard mask layer (not shown) are formed over the lower gate conductive layer. The gate hard mask layer, the upper gate conductive layer, and the lower gate conductive layer are patterned using a gate mask (not shown) as an etching mask to form a gate structure 190 comprising a stacked structure of a gate electrode 170 and a gate hard mask layer pattern 180. Gate spacers (not shown) are formed on sidewalls of the gate structure 190. Impurity ions are injected into the semiconductor substrate 110 at both sides of the gate structure 190 including the gate spacer to form source/drain regions 195. In one embodiment, a process for cleaning the exposed semiconductor substrate 110 can be performed by a solution including HF before the formation of the gate insulating film 160. In addition, the gate insulating film 160 is formed using a gas including O₂, H₂O, O₃ or combinations thereof with its thickness ranging from about 1 nm to about 10 nm. In another embodiment, the lower gate conductive layer is formed of a polysilicon layer doped with impurity ions such as P or B. Here, the doped polysilicon layer is formed by implanting impurity ions into an undoped polysilicon or by using a silicon source gas and an impurity source gas including P or B. In addition, the upper gate conductive layer is selected from the group consisting of a titanium (Ti) layer, a titanium nitride (TiN) film, a tungsten (W) layer, an aluminum (Al) layer, a copper (Cu) layer, a tungsten silicide (WSi_(X)) layer or combinations thereof.

In addition, subsequent processes such as a process for forming a landing plug, a process for forming a bit line contact and a bit line, a process for forming a capacitor, and a process for forming an interconnect may be performed.

As described above, the semiconductor substrate and method for fabricating the same in accordance with an embodiment of the present invention provides forming a stepped recess channel region including vertical SOI channel structures on sidewalls of both device isolation structures under a gate structure, thereby obtaining relatively large driving current. In addition, the lowering of threshold voltage due to drain voltage, body effect, and gate On/Off characteristics can be improved because of SOI structure. According to the present invention, the semiconductor substrate has extendibility capable of securing substantial channel area of the device despite shrinkage of its design rules. The conventional gate mask may be used for forming the recess region. As a result, the process cost can be saved. The process is made simple, which results in decreasing the number of defected devices.

The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the type of deposition, etching polishing, and patterning steps described herein. Nor is the invention limited to any specific type of semiconductor device. For example, the present invention may be implemented in a dynamic random access memory (DRAM) device or non-volatile memory device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims. 

1. A semiconductor device comprising: a device isolation structure formed in a semiconductor substrate to define an active region; a stepped recess channel region including vertical silicon-on-insulator (SOI) channel structures formed in the active region, wherein the vertical SOI channel structures are disposed at sidewalls of the device isolation structure in a longitudinal direction of a gate region; and a gate structure disposed over the stepped recess channel region of the gate region.
 2. The semiconductor device according to claim 1, wherein a thickness of the vertical SOI channel structure ranges from about 1 nm to about 50 nm in a horizontal direction.
 3. The semiconductor device according to claim 1, wherein a depth of the vertical SOI channel structures from the upper step of the stepped recess channel region to its lower step ranges from 5 nm to 200 nm in a vertical direction.
 4. The semiconductor device according to claim 1, wherein a gate insulating film is disposed over the active region including the stepped recess channel.
 5. The semiconductor device according to claim 4, wherein the gate structure corresponding to the gate region is disposed over the gate insulating film.
 6. The semiconductor device according to claim 1, wherein the gate structure includes a stacked structure of a gate electrode filling the stepped recess channel region and a gate hard mask layer pattern.
 7. The semiconductor device according to claim 6, wherein the gate electrode includes a stacked structure of a lower gate electrode and an upper gate electrode.
 8. The semiconductor device according to claim 7, wherein the lower gate electrode is a polysilicon layer doped with impurity ions.
 9. The semiconductor device according to claim 8, wherein the impurity ions include phosphorus (P) or boron (B).
 10. The semiconductor device according to claim 8, wherein the upper gate electrode is selected from a group consisting of a titanium (Ti) layer, a titanium nitride (TiN) film, a tungsten (W) layer, an aluminum (Al) layer, a copper (CU) layer, a tungsten silicide (WSi_(x)) layer or combinations thereof. 